1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits, including advanced transistor elements that comprise strain-inducing semiconductor alloys and gate structures of increased capacitance including a high-k gate dielectric of increased permittivity.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2), and the bike.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
After forming sophisticated gate structures including a high-k dielectric and a metal-based gate material, however, high temperature treatments may be required, which may result in a shift of the work function and a reduction of the permittivity of the gate dielectric, which may also be associated with an increase of layer thickness, thereby offsetting many of the advantages of the high-k dielectric in combination with the metal material. It is believed that the deterioration of the high-k metal gate is substantially caused by the incorporation of oxygen and a respective oxygen diffusion within the high-k dielectric material, wherein the oxygen diffusion may be fed by oxygen contained in the ambient that may come into contact with the high-k dielectric during the processing of the devices. Since, for instance, hafnium- and zirconium-based oxides grow very fast due to the high affinity to oxygen diffusion even at moderately high temperatures, a significant modification of the characteristics of the high-k dielectric material may be observed, for instance an increased layer thickness and thus a reduced dielectric constant, which may even further be pronounced at moderately high temperatures of approximately 950-1300° C. as may typically be used during activation treatments and the like.
In addition to a significant modification of the high-k dielectric material, also the work function of the metal in the gate stack may be shifted towards the center of the band gap, thereby modifying the threshold voltage of respective transistors. Due to the high oxygen affinity of the high-k dielectric material, the gate stack is usually encapsulated after the patterning process in order to avoid or at least significantly reduce any contact of oxygen contained in the process ambience and the like to enhance stability of the high-k dielectric material and the respective metals in the gate stack. For this purpose, silicon nitride has proven to be a promising material due to its oxygen blocking characteristics. Hence, in typical conventional process flows, a silicon nitride liner with a thickness in the range of approximately 1-5 nm may be formed on exposed surface areas of the patterned high-k gate stack, wherein appropriate deposition techniques are used so as to not unduly affect device characteristics and/or the subsequent manufacturing steps. For example, well-established low pressure chemical vapor deposition (LPCVD) techniques may be applied for forming the silicon nitride liner.
In addition to providing sophisticated gate electrode structures by using high-k dielectric materials and metal-containing gate electrode materials, other approaches have been developed in order to enhance transistor performance for a given gate length and a thickness of a gate dielectric material. For example, by creating a certain strain component in the channel region of the transistor elements, the charge-carrier mobility and thus the overall conductivity of the channel may be enhanced. For a silicon material having a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a (110) equivalent direction, the creation of a tensile strain component in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain component in the current flow direction may increase hole mobility and thus provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past which may per se require a complex manufacturing sequence for implementing the various strain-inducing techniques. For example, one promising approach that is frequently applied is the incorporation of a compressive strain-inducing semiconductor alloy in the drain and source areas of P-channel transistors. For this purpose, in an early manufacturing stage, cavities are selectively formed adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. Additionally, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose the gate electrode material to the etch ambient for forming the cavities and also for providing an efficient growth mask during the selective epitaxial growth process, in which a desired semiconductor alloy may be grown on a crystalline substrate material, while a significant deposition of material on dielectric surface areas may be suppressed by appropriately selecting the corresponding process parameters. After forming the strain-inducing semiconductor alloy, the corresponding spacer structure and a cap layer encapsulating the gate electrode of the P-channel transistor may be removed along with the spacer layer that covers the N-channel transistors. Thereafter, the further processing may be continued by forming drain and source regions so as to complete the basic transistor configuration.
A corresponding strain-inducing mechanism is a very efficient concept for improving transistor performance and thus a combination with sophisticated gate electrode structures on the basis of high-k dielectric materials and metal gate electrodes is highly desirable. However, it turns out that the combination of both complex process sequences may cause integrity issues with respect to the sensitive high-k dielectric material, since the corresponding protection liner may be unduly exposed to reactive etch ambient, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, an insulating carrier material and the like, above which is formed a silicon-based semiconductor layer 102. In and above the semiconductor layer 102, sophisticated transistor elements 100P, 100N are to be formed on the basis of a strain-inducing mechanism and on the basis of a sophisticated gate electrode structure. In the manufacturing stage shown in FIG. 1a, the transistors 100P, 100N comprise a first gate stack 110P and a second gate stack 110N, respectively, which both may have incorporated a high-k gate dielectric material in combination with an appropriately selected metal-containing electrode material. For example, the gate stacks 110P, 110N may both comprise a basic oxide material 111 of reduced thickness, for instance with a thickness of approximately 1 nm or less, to provide a well-established interface with corresponding channel regions 103 located below the corresponding gate stacks 110P, 110N. Moreover, a high-k dielectric material, such as one of the materials specified above, for instance in the form of hafnium oxide, is formed on the basic oxide layer 111, as indicated by 112. For example, a thickness of the high-k dielectric material 112 may range from 1-2 nm, when hafnium oxide is used. Furthermore, the first gate stack 110P comprises a metal-containing electrode material 113P, the work function of which may be appropriately adjusted so as to obtain a desired threshold voltage for the P-channel transistor 100P. Similarly, the gate stack 110N has formed on the high-k dielectric material 112 an appropriately selected gate electrode material 113N with a required work function to comply with the device requirements of the transistor 100N. For example, the materials 113P, 113N may be provided on the basis of a titanium nitride material, wherein an additional material composition or a corresponding adaptation of the material characteristics may be performed in one of the gate stacks 110P, 110N. Furthermore, an additional gate electrode material 114, for instance in the form of polysilicon, is typically provided in order to obtain a desired height of the gate stacks 110P, 110N, for instance with respect to the further processing, when corresponding drain and source regions are to be formed on the basis of implantation processes, in which a certain degree of ion-blocking effect of the gate stacks is required for protecting the channel regions 103. Furthermore, a liner material 115 followed by a cap layer 116 is formed above the material 114. The liner material 115 is typically comprised of silicon dioxide, while the cap layer 116 is formed of silicon nitride. As previously explained, in view of enhanced integrity of the sensitive high-k dielectric material 112 and the electrode materials 113P, 113N, which have to be stabilized during the further processing in view of any threshold voltage variabilities, a protection liner 104 comprised of silicon nitride is formed in particular on sidewalls of the gate stacks 110P, 110N. Additionally, an etch stop liner 105, comprised of silicon dioxide, and a spacer layer 106 are formed above the transistors 100P, 100N. In the manufacturing stage shown, an etch mask 107 is provided to cover the transistor 100N, above which the spacer layer 106 is to be maintained during a subsequent patterning sequence for forming cavities in the transistor 100P.
The semiconductor device 100 is typically formed on the basis of the following process. After forming respective isolation structures (not shown) and defining an appropriate basic dopant profile in the semiconductor layer 102 as is required for the different transistors 100P, 100N, the gate stacks 110P, 110N may be formed. To this end, the basic oxide layer 111 is typically formed by using sophisticated oxidation processes, followed by the deposition of the high-k dielectric material 112. Thereafter, a corresponding process sequence is applied in which the materials 113P, 113N are selectively provided in accordance with the corresponding work functions in view of adjusting the threshold voltage of the corresponding transistors 100P, 100N. For instance, an appropriate first metal-containing material may be deposited and may be removed from above one of the transistors, such as transistor 100P, followed by the deposition of a further material having appropriate electronic characteristics for the transistor 100P. Next, the polysilicon material may be deposited, for instance in combination with materials 115 and 116, which are subsequently patterned by using sophisticated lithography and etch techniques. Next, the silicon nitride liner 104 is formed with a thickness of approximately 1-5 nm by using sophisticated deposition techniques, such as atomic layer deposition (ALD), thermally activated chemical vapor deposition (CVD) and the like, as is also previously described. Thereafter, the silicon dioxide liner 105 is deposited, followed by the deposition of the spacer material 106. Finally, the etch mask 107 is provided by using well-established lithography techniques.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which the spacer layer 106 is patterned into a corresponding spacer element 106A, which may be accomplished by using well-established anisotropic etch techniques, in which silicon nitride material is etched selectively to silicon dioxide material. Thereafter, exposed portions of the liner 105 and of the liner 104 are removed by additional etch steps. Furthermore, the mask 107 (FIG. 1a) is removed prior to or after a corresponding etch process for forming cavities in the exposed portion of the semiconductor layer 102 of the transistor 100P. After forming the corresponding cavities, exposed portions of the device 100 are prepared for a subsequent selective epitaxial growth process, requiring corresponding wet chemical cleaning processes. Thereafter, an appropriate semiconductor alloy may be deposited selectively within the previously-formed cavities using well-established deposition recipes.
FIG. 1c schematically illustrates the semiconductor device 100 after the epitaxial growth process. Hence, a semiconductor alloy 108, for instance in the form a silicon/germanium mixture, is formed in the semiconductor layer 102 laterally adjacent to the gate stack 110P and offset therefrom by the spacer 106A.
FIG. 1d schematically illustrates the device 100 during an etch process 109 that is typically performed on the basis of hot phosphoric acid in order to remove the cap layer 116 of the gate stack 110P and also the spacer layer 106 formed above the transistor 100N. Hot phosphoric acid is a well-established chemical agent for removing silicon nitride selectively to silicon dioxide and silicon material. During the etch, process 109, a certain consumption of the liner 104 may occur in the transistor 100P, as indicated by 104P, wherein, however, reliable coverage of the sidewall portions of the gate stack 110P may be maintained. On the other hand, the spacer layer 106 is removed, wherein the liner material 105 reliably covers the liner 104, however, also reliably covers the cap layer 116 of the gate stack 110N. Consequently, a further masked etch process is performed in order to remove the cap layer 116 of the stack 110N.
FIG. 1e schematically illustrates the semiconductor device 100 with an etch mask 121 covering the transistor 100P while exposing the transistor 100N to an etch ambient 120, which may be established on the basis of plasma-assisted etch chemistry in order to remove exposed portions of the liners 104N, 105 from horizontal device areas, thereby exposing the cap layer 116 of the gate stack 110N. Consequently, during the etch process 120, liner 105 may be substantially maintained at sidewalls of the gate stack 110N, since exposure to the etch ambient 120 may be restricted to a moderately short etch time, since the initial thickness of the liners 104, 105 is moderately small. Furthermore, by restricting the etch time of process 120, undue material erosion of the exposed portion of the semiconductor layer 102 in the transistor 100N may be maintained at an acceptable level. Thereafter, the etch mask 121 is removed or may be maintained during a further etch process for removing the cap layer 116 of the stack 110N.
FIG. 1f schematically illustrates the semiconductor device 100 wherein a corresponding etch process 122, may be performed on the basis of hot phosphoric acid due to the enhanced selectivity with respect to silicon dioxide and silicon, as already previously discussed. However, during the etch process 122, exposed portions of the liner 104N may further be attacked and thus removed, thereby possibly exposing the sensitive high-k dielectric material 112 in the gate stack 110N. That is, due to the sequence of etch processes 120, 122, undue consumption of the liner 104N may occur, which may thus result in reduced integrity of gate stack 110N, while a corresponding undue exposure of sensitive materials in the gate stack 110P may be less critical, even if exposed to the etch ambient 122, since the corresponding liner material 104P may have an increased lateral extension at the bottom of the gate stack 110P.
As a consequence, during the further processing, i.e., forming drain and source regions on the basis of an appropriately-designed spacer structure and performing corresponding high temperature processes, integrity of the lower portion of the gate stack 110N may not be guaranteed, which may result in a significant threshold viability after finalizing the transistor 100N. Consequently, although advanced process techniques are used, for instance by incorporating the strain-inducing semiconductor alloy 108 for the transistor 100P and implementing a sophisticated gate electrode structure, the finally-obtained gain in performance may be less due to a corresponding threshold variation, in particular of the N-channel transistor 100N.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.